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An extremely low temporal noise and wide dynamic range CMOS image sensor is developed using low-noise transistors and high gray-scale resolution (17b) folding-integration/cyclic ADC. Two types of pixel are designed. One is a high conversion gain (HCG) pixel with removing the coupling capacitance between the transfer gate and the floating diffusion, and the other is a pixel for wide dynamic range (WDR)...
A 15 b power-efficient pipeline A/D converter using capacitance-coupling non-slewing amplifiers is presented. A modified 1.5b/stage transfer curve combined with the non-slewing amplifier is useful for the error corrections of incomplete settling error. The relationship between the input signal and the incomplete settling errors can be linearized and the errors can be corrected in digital domain with...
A pre-charging technique to improve the settling response of pipeline stages is demonstrated in a Mbit pipeline A/D converter (ADC). The prototype ADC fabricated in a 0.25 mum CMOS process consumes 102 mW at 30 MSample/s. Measured SNDR and SFDR are 70.7 dB and 82.8 dB, respectively.
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