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HfO2 gate dielectric is fabricated by atomic layer deposition on an n-type germanium (Ge) substrate to form p-type Ge MOS capacitors. Three solution-based chemical treatments of the Ge surface using propanethiol, octanethiol and (NH4)2S solutions respectively as well as post-metallization annealing are investigated to improve the interface quality of HfO2 gate dielectric on the Ge substrate. Experimental...
This paper describes the development of work function measurements using Kelvin probe force microscopy (KPFM) on semiconductor materials including high-κ/metal gate layers. We show how the choice of substrate and/or underlying films affects work function quantification. Other influences on work function measurement such as sample aging, humidity, and measurement mode were also studied. Finally, TiAl...
This paper describes the development of work function measurements using Kelvin probe force microscopy (KPFM) on semiconductor materials including high-κ/metal gate layers. We show how the choice of substrate and/or underlying films affects work function quantification. Other influences on work function measurement such as sample aging, humidity, and measurement mode were also studied. Finally, TiAl...
This paper reports on the low-dose-rate radiation response of Al-HfO2/SiO2–Si MOS devices, where the gate dielectric was formed by atomic layer deposition with 4.7 nm equivalent oxide thickness. The degradation of the devices was characterized by a pulse capacitance-voltage (CV) and on-site radiation response techniques under continuous gamma ($\gamma $ ) ray exposure at a relatively low-dose-rate...
Titanium-aluminum (TiAl) alloys are the industry standard source for work function tuning of High-K nMOS transistors in the gate-last process architecture. When aluminum is used as a metal gate fill material, the TiAl alloy also serves as a diffusion barrier against excess aluminum migration into the work function metal and dielectric layers. However, the formation of the TiAl alloy by annealing titanium...
Copper metal gate has been introduced in logic CMOS processes starting from the 45-nm technology node. With the skin depth of about 270 nm at 60 GHz for copper, the DC end-to-end resistance of the copper gate electrode is found to be Rdc ≈ 9 Ω for a 45-nm MOSFET with W/L = 30 and it is a good estimation of the actual effective resistance Rac with less than 1% error. Rac of copper-gate electrode with...
The effect of parasitic capacitances and resistances on RF performance is investigated for a recently reported 30-nm transistor with regrown source and drain structure which is to reduce the access resistance in nanoscale MOSFETs. The relatively large lateral parasitic capacitances from the gate electrode to the regrown source and drain regions are quantitatively determined to estimate their impact...
A recently reported nanometre-scaled MOSFET structure with regrown source and drain is examined. The parasitic circuit elements are identified and quantitatively determined to estimate their impact on the transistor's RF performance. Due to the relatively large lateral parasitic capacitances from the gate electrode to the regrown source and drain regions, the current gain cut-off frequency fT of such...
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