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A porous template has been reported to reduce defect density and strains, and hence to improve the properties of gallium nitride (GaN) deposited on it. On the other hand, creating a porous aluminum nitride (AlN) template is challenging and, therefore, reports on it are scarce. In this work, the material quality of a polycrystalline GaN layer was improved by manipulating the etching time of the porous...
This paper reports on the design, implementation, and characterization of a trench-filled capacitor in complementary Metal-Oxide-Semiconductor (CMOS) grade silicon. In order to achieve high capacitance value in MOS capacitor, trench technology is applied to improved capacitance. The simulation executed by using Synopsys's Sentaurus TCAD. A C-V measurement was done between two different structures...
In this work, we investigate the impact of varying silicon-body thickness, Tsi i.e 5 nm, 7 nm, 10 nm and 12 nm on the digital figures-of-merit performance of Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs of 10 nm gate length with different ground plane (GP) structures under the double-gate (DG) operation-mode. We show that degradations of the digital characteristics i.e DIBL, subthreshold-slope...
In this work, we investigate the impact of using different gate dielectric materials i.e HfO2 and Si3N4 as compared to the conventional SiO2 with equivalent oxide thickness (EOT) of 1.2 nm on the digital and analog performance of UTBB SOI MOSFETs of 10 nm gate length with different ground plane (GP) structures under the double-gate (DG) operation-mode by numerical simulations. It is found that Si3N4...
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