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Embedded SRAM elements are becoming the main detractor of the overall System-on-Chip (SoC) yield. To increase the reliability of embedded SRAMs, the use of Error Correction Code (ECC) has been widely adopted. Depending on the implemented ECC scheme, SRAMs can detect/correct the presence of one or more transient errors during the mission time. In this paper, we investigate the possibility of exploiting...
Managing the power consumption of circuits and systems is challenging not only during functional operations but also during manufacturing test. This paper discusses industrial practices in this area. It is organized into three main parts. First, we give necessary background and discuss issues arising from excessive power dissipation during test application. Then, we provide an overview of industrial...
Functional test guarantees that the circuit is tested under normal conditions, thus avoiding any over-as well as under-test issues. This work is based on the use of Software-Based-Self-Test that allows a special application of functional test to the processor-based systems. This strategy applies the so-called functional test programs that are executed by the processor to guarantee a given fault coverage...
Selecting the ideal trade-off between reliability and cost associated with a fault tolerant architecture generally involves an extensive design space exploration. Employing state-of-the-art susceptibility estimation methods makes it unscalable with design complexity. In this paper we introduce a low-cost susceptibility analysis methodology that helps identifying the most vulnerable circuit elements...
Functional test guarantees that the circuit is tested under normal conditions, thus avoiding any over-as well as under-test. This work is based on the use of Software-Based-Self-Test that allows a special application of functional test to the processor-based systems. This strategy applies the so-called functional test programs that are executed by the processor to guarantee a given fault coverage...
Approximate computing has been adopted as a promising approach to energy-efficient design of digital systems. Actually the straightforward idea is to lower the supplied voltage level until errors appear. These errors can be "implicitly" tolerated since the application accepts some loss of quality or optimality in the computed result(s). This paper aims at targeting applications that cannot...
This paper presents a hybrid power modeling approach based on an efficient library characterization methodology and an effective power estimation flow to accurately assess gate-level power consumption in a faster way. As a case study, we apply the proposed approach on 28nm Fully-Depleted Silicon On Insulator technology.
Fault-tolerant architectures have been widely used in industry to prevent circuit reliability from becoming a bottleneck for the development of robust high-performance and low-power systems. One such solution is a Hybrid Fault-Tolerant Architecture that offers benefits such as low power and lifetime reliability improvement. However, it has been identified that there is room of improvement in efficiency...
Increasing vulnerability of transistors and interconnects due to CMOS technology scaling is continuously challenging the reliability of future electronic circuits and systems. Lifetime reliability is gaining attention over performance as a design factor even for lower-end commodity applications. In this paper we propose an effective hybrid fault-tolerant architecture able to deal with permanent and...
High power consumption during at-speed delay fault testing may lead to yield loss and premature aging. On the other hand, reducing too much test power might lead to test escape and reliability problems. Thus, to avoid these issues, test power has to map the power consumed during functional mode. Existing works target the generation of functional test programs able to maximize the power consumption...
Power-gating techniques have been adopted so far to reduce the static power consumption of an Integrated Circuit (IC). Power-gating is usually implemented by means of several power switches. Manufacturing defects affecting power switches can lead to increase the actual static power consumption and, in the worst case, they can completely isolate a functional block in the IC. Thus, efficient test and...
This paper proposes a novel approach for the generation of test patterns suitable for detecting Gate Delay Faults (GDFs). The key idea lies in associating any single Gate Delay Fault to a set of Transition Delay (TD) Faults, and exploiting this relationship to produce effective patterns. The approach encompasses several steps: once a Gate Delay Fault is translated into a set of equivalent Transition...
With the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. Several works analyze the impact of intra-cell defects w.r.t. the test quality. However, to the best of our knowledge, none of them target intra-cell defects affecting scan flip-flops. This paper presents an evaluation of the effectiveness of the ATPG test patterns in terms of intra-cell...
This work presents a single-supply SPARC 32b V8 microprocessor designed with Ultra Low Voltage (ULV) adapted standard cells and memories, aiming at low energy operation and stand by power. The microprocessor, equipped with 10 Transistors ULV bitcell 8KB SRAM cache, has been fabricated in Fully Depleted Silicon On Insulator (FDSOI) 28nm technology. A comparative analysis with similar implementations...
In this paper, we investigate the generation of diagnostic test vectors targeting the intra-cell defects. Experimental results carried out on an industrial circuit show that we actually increase the diagnosis resolution by adding few more diagnostic test patterns.
This paper presents an evaluation framework for functional programs. Programs are evaluated w.r.t. functional and structural metrics. The goal is to verify if the targeted functional programs can be re-used for verification and test purposes.
In this paper we propose a novel Power Supply Noise (PSN) sensor. It is based on timing uncertainty measure. Compared to state of the art it allows to measure the PSN events in more accurate way. The proposed sensor is actually under validation and patent reviewing process.
3D-IC test becomes a challenge with the increasing number of TSVs and demands for effective 3D aware test techniques. In this work, we propose a timing aware model to capture delay variations on a path due to resistive open TSVs. The key idea is to analytically model delay and apply our correlation-based resistive open TSV detection method to attain path delay fault coverage. We propose two methods...
Through-Silicon-Vias (TSVs) are the key enablers of 3D integration technology. Therefore, the reliability of 3D-ICs rely on the quality of TSV testing. TSVs are prone to defects that may introduce small delay variations that can cause quality and reliability issues. Moreover, physical and electrical conditions, such as TSV dimensions, coupling and IR-drop, may affect path delay variations and consequently...
With the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. In this paper we propose a defect grading tool able to evaluate the efficiency of the applied test set. The test set efficiency is quantified w.r.t. the intra-cell defect coverage and the intra-cell diagnosis resolution.
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