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A novel architecture of the configurable Distributed Random Access Memory (RAM) logic based on Look-Up Tables (LUTs) in the Logic Block (LB) is proposed and implemented in a tile-based FPGA manufactured with a 0.5μm SOI-CMOS logic process. The Distributed RAM can be configured in two modes: Single-Port RAM and Dual-Port RAM. Due to its resource abundance and low latency the Distributed RAM can complement...
A large and sudden current called surge current is always induced due to the momentary supply current through a low resistance path to ground when filed programmable gate array (FPGA) power on. This surge current will request the power supply of FPGA to source more current to meet this instantaneous demand or complicate the power management system of FPGA in order to succeed in powering up FPGA. Therefore,...
A novel logic block circuit consisting of two multi-mode logic cells is proposed for the design of a tile-based FPGA fabricated with a 0.5μm SOI-CMOS logic process. Each logic cell contains two 3-LUTs. The proposed 3-LUT based logic cell circuit increases logic density by about 12% compared with a traditional 4-LUT implementation. The logic block can be used in two functional modes: LUT mode and Distributed...
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