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Network-on-Chip (NoC) are well-established for scalable on-chip communication, but technology generations of 22~nm and below, as well as aggressive voltage scaling to reduce NoC power consumption, introduce new variability challenges resulting in errors on wires and registers. Based on the probabilities of single bit flips, this paper focuses on the expected end-to-end packet error probabilities in...
Single Root I/O Virtualization (SR-IOV) is an extension to the PCI Express (PCIe) standard that allows virtual machines (VMs) to directly access shared I/O devices without host involvement. This enabled SR-IOV to become the best-performing solution for virtual I/O to date, which lead to its commercial adoption, e.g., In the Amazon EC2. On the downside, a malicious VM can exploit the direct access...
Power densities and thermal hotspots are a major concern for the dependability of future multi-processor systemon- chip. They can lead to transient faults affecting the functionality in the short term and can cause permanent damage of a device. The dependability problem can be tackled on different layers such as technology hardening or application awareness. This work is based on an approach that...
In a shared-memory based tiled many-core system-on-chip architecture, memory accesses present a huge performance bottleneck in terms of access latency as well as bandwidth requirements. The best practice approach to address this issue is to provide a multi-level cache hierarchy and a suitable cache-coherency mechanism. This paper presents a method to increase the memory access performance in distributed-directory-coherency-protocol...
Network-on-Chip (NoC) have become favorable for on-chip communication, especially with the ever rising number of communication partners in future manycore system-on-chip. NoCs that are based on mesh topologies with dimension-routing are well-established as they scale well with the increasing number of communication partners and allow efficient router design. To be able to serve application demands...
Tiled manycore architectures have become dominant for the integration of tens or even a hundred processor cores on a chip. While commercial products are increasingly available, research on the hardware of such platforms and especially prototyping often rely on building such a platform from scratch or is bound to abstract simulation. In this paper we present the Open Tiled Manycore System-on-Chip (Op-TiMSoC)...
Future manycore Systems-on-Chip will integrate tens or even hundreds of cores. Tiled architectures have come to the focus of research and industry. Such platforms integrate processing cores in clusters and connect those ‘tiles’ with a global interconnect. Message passing programming models are favored to program such complex distributed memory systems. A significant performance overhead is involved...
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