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Fast NBTI recovery experiments performed for alternating DC and AC stress modes show that recovery behavior is strongly influenced by degradation history. Proper modeling of PMOS recovery in circuits as well as projections of product lifetime must comprehend the interaction of DC and AC usage states.
We present an experimental study of the emission from electrostatic discharges between dielectrics, focusing on the role of extended conductors close to the discharge region. In the absence of an antenna capacitively coupled to the arc, the electromagnetic emission is negligible, while with rod antennas of di erent lengths electromagnetic transients can be clearly measured. Analyzing the spectrum...
We present an experimental study of the emission from electrostatic discharges between dielectrics, focusing on the role of extended conductors close to the discharge region. In the absence of an antenna capacitively coupled to the arc, the electromagnetic emission is negligible, while with rod antennas of different lengths electromagnetic transients can be clearly measured. Analyzing the spectrum...
Gate oxide breakdown is a key mechanism limiting IC lifetime. Breakdown is typically characterized on test capacitors, but estimating product reliability from such results requires making a number of often-untested assumptions. This work compares the predictions of capacitor-based models to results from accelerated lifetest of logic CPU products. For the technology studied, lifetest failure rate was...
The focus of this work is to demonstrate the effect of mechanical stress in the channel on the impact ionization rate (IIR) and on hot carrier reliability for both NMOS and PMOS devices. In addition, this study will explain the reason for the wide disagreement between published reports on this behavior. It is shown for the first time that the IIR reaches a maximum value with strain for NMOS and then...
PMOS transistor degradation due to negative bias temperature instability (NBTI) has proven to be a significant concern to present CMOS technologies. This is of particular importance for analog applications where the ability to match device characteristics to a high precision is critical. Analog circuits use larger than minimum device dimensions to minimize the effects of process variation, leaving...
Erratic bit phenomena have been reported in advanced flash memories, and have been attributed to trapping/detrapping effects that modify the threshold voltage. This paper describes for the first time the observance of erratic behavior in SRAM Vmin, defined as the minimum voltage at which the SRAM array is functional. Random telegraph signal (RTS) noise in the soft breakdown gate leakage is shown to...
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