In this work, we present the technological constrains and limitations in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space that take into account the intrinsic off-current, the sub-threshold swing and the drain induced barrier lowering is investigated with respect to key technological parameters. This work could serve as a guideline for technology...
This paper reports an alternative simple fabrication process for twin gate junctionless Vertical Slit Field Effect Transistors. N-type devices have been successfully manufactured on SOI substrates with a doping density 5×1018 atoms/cm3. The devices demonstrate up to six decades of Ion/Ioff ratio and a sub-threshold swing of 90 mV/decade relative to a slit width of approximately 10 nm.
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