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Instruction fetching usually consumes more than 50% of total power in embedded processors. In DSP applications, instructions to be fetched may come from loops mostly. This paper proposes a loop unit of low-power microarchitecture for nested looping and it is fully compatible with RISC pipeline architecture. A loop instruction set is designed to finish different kinds of loops. Branching, jumping and...
For next-generation audio applications, the dominant trends are much higher sample rate, larger word length and more audio channels for playback audio data. Traditional DSPs or embedded processors are inefficient for such kinds of applications because of their non-specific or limited computing capabilities as well as the on-chip memory architectures. In this paper, an embedded audio processor aiming...
Rich requirements from high definition television (HDTV) decoder argue the supports of complex architecture and operating system (OS). As an embedded system, multi-processor system-on-a-chip (MPSoC) is an ideal implementation of the decoder. Open source OS has many advantages to be ported to embedded fields. This paper describes the detailed process of its porting, including building environment,...
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