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Addition of Pt to Ni silicide produces a robust [NixPt(l-x)]Si, which shows an improved morphological stability, an important reduction in encroachment defect density, a reduced tendency to form NiSi2 and significant variations in monosilicide texture without degrading the device performance or the yield of high-performance 65 nm SOI technologies.
In this paper we present enhancements in transistor performance and manufacturability of a high performance 65nm node SOI transistor by the combination of reduced RTA temperature and laser spike anneal (LTRTA+LSA) achieved through simultaneous optimization of offset spacer and extension/halo. DC NFET drive current is increased by 10% to a value of 1120 muA/mum (1220muA/mum if 9% NFET SOI self-heating...
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