The single event effects hardening and heavy-ion testing of a radiation-hardened Flash-based field programmable gate array, RTG4, are presented. The hardened logic circuits include fabric flip-flops, fabric SRAM, global clocks, PLL, and SERDES. SEL is hardened for the whole chip. Lastly, the inspace programming is hardened as the consequence of the above hardening activities. Test results show the...
Reliability test results of data retention and total ionizing dose (TID) in 65 nm Flash-based field programmable gate array (FPGA) are presented. Long-chain inverter design is recommended for reliability evaluation because it is the worst case design for both effects. Based on preliminary test data, both issues are unified and modeled by one natural decay equation. The relative contributions of TID...
Heavy-ion beam is used to perform Single Event Effects testing on the Flash-based and radiation hardened FPGA, the RT4G150 device. Soft errors due to SEU and SET in the fabric Flip-Flops and PLL generated clocks are measured and analyzed. SEFIs in PLL and SERDES are also observed.
The newly introduced radiation-tolerant flash-based FPGA, RTG4, uses a novel configuration cell design composed of a NMOS switch controlled by a totem pole p-channel flash and n-channel flash construction. Its radiation tolerance is far superior to that in the present available Flash-based FPGA. This paper describes the radiation hardening by design (RHBD) process for the new flash-based configuration...
Reliability test results of data retention and total ionizing dose (TID) in 65 nm Flash-based field programmable gate array (FPGA) are reviewed. Long-chain inverter design is recommended for reliability evaluation because it can detect degradations of both programmable and erased Flash cells. All the reliability issues are unified and modeled by one natural decay equation.
In this work 3D-TCAD simulation is used to investigate and harden single event latch-up (SEL) occurring in embedded SRAMs, in both 130 nm and 65 nm Flash-based Field Programmable Gate Arrays (FPGAs). The methodology to perform accurate SEL simulations on realistic designs suitable for high volume manufacturing is presented. One important new finding is that depending on the technology node, the number...
TID and SEE characterization of Microsemi's 4th generation RTG4 flash-based FPGA is presented. The radiation performance of RTG4 is compared to SmartFusion2, Microsemi's 4th generation commercial flash-based FPGA.
SET and SEFI characterization of the SmartFusion2 flash-based FPGA under heavy ion irradiation is presented. Functional blocks such as the PLL and Microcontroller Sub System are characterized and presented.
SmartFusion2 Flash-based Reprogrammable FPGAs are Neutron beam tested. Results confirm immunity of SEL and configuration upset with an elevated temperature approximately 95 ºC. SEU is discussed for the Fabric Logic, Global logic, SRAM, PLL and SEFI on the MSS.
New 65 nm flash-based field programmable gate array with system-on-chip capability is introduced. We present recent Total Ionizing Dose tests results on Smart Fusion 2 Flash-based FPGAs. TID effects at the device and product level are presented and discussed.
In order to investigate frequency and architectural effects on Single Event Upset cross sections within RTAX-S FPGA devices, a novel approach to high speed testing is implemented. Testing was performed at variable speeds ranging from 15 MHz to 150 MHz
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