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High-frequency characteristics of Lg = 60 nm In0.7Ga0.3As MOS-high-electron-mobility transistor (HEMTs) with a 3 nm aluminium oxide grown by atomic-layer-deposition is reported. Fabricated In0.7Ga0.3As MOS-HEMTs with Lg = 60 nm exhibit subthreshold-swing (SS) = 89 mV/dec., drain-induced-barrier-lowering = 98 mV/V, gm_max = 1.1 mS/μm, fT = 187 GHz and fmax = 202 GHz at VDS = 0.5 V. The high-frequency...
Recently long-channel PMOS transistors are being used in delay circuits to increase delay time. Negative Bias Temperature Instability (NBTI) has channel length dependency which shows that long-channel devices degrade more than short channel devices. We suggest a source underlap structure with short channel transistor to solve this problem. We confirmed the short-channel device with underlap structure...
Gate oxide and interface trap charges are critical parameters for device reliability and their generation and recovery are investigated under AC and DC oxide field stress on n-channel MOSFETs by C-V, I-V, and CP measurements. The interface traps generation is the same under both DC and AC stress but oxide charge trap generation is higher at AC stress than DC stress. The oxide charge and interface...
A new and accurate approach to gate oxide reliability measurements for the determination of the gate oxide quality and lifetime estimation on MOSFET is presented. An accurate gate oxide thickness calculation by gate current provides oxide thickness variations better than conventional CV measurement. A gate oxide quality by gate current analysis is well correlated to the time dependent dielectric breakdown...
We have studied key parameters for controlling threshold voltage (Vth) variation and strain maintenance of gate first SiGe channel pMOSFETs. By overcoming 1) Ge diffusion and 2) strain relaxation during source/drain activation, we for the first time demonstrate high Ge% (50%) SiGe channel with millisecond flash anneal. Optimizing the thermal budget with millisecond anneal keeps the Vth variation same...
Charge trapping and wearout characteristics of self-aligned enhancement-mode GaAs nMOSFETs with silicon interface passivation layer and HfO2 gate oxide are systematically investigated at various time scales (from micro-seconds to seconds). Unlike high-kappa on silicon devices, both bulk trapping and interface trapping affect the PBTI (positive bias temperature instability) characteristics of nMOSFETs...
We report on new observations of hot carrier (HC) degradation in strained Si/Si1-xGex(x = 0.2 to 0.5) p-MOSFETs. By using low voltage current-voltage measurement coupled with carrier separation, we are able, for the first time, to easily distinguish the energy distribution of the interface traps. High-K dielectrics on SiGe p-channel show higher interface traps generation located close to conduction...
Research on high-k (HfO2) materials has been expanded significantly. However, MOSFETs with high-k gate dielectrics on silicon still have several problems with relatively low mobility of high-k devices in thin EOT regime compared to the universal curve. In this work, as an alternative of silicon substrate, InP and In0.53Ga0.47As has been studied. W e present the material and electrical characteristics...
A metal/high-k gate stack with P-type band edge effective work function (EWF) of 5.1-5.2 eV is achieved through optimization of a Ru-Al based metal electrode. The critical factors controlling the high EWF values are found to be Al incorporation at the high-k/SiO2 interface and stabilization of the conductive RuO2 layer at the electrode/high-k interface. A pMOSFET with a fully optimized RuAl metal...
Partially-insulated oxide (PIOX) layers are implemented under the source/drain region in bulk FinFETs. The improved short channel effect by controlling the sub-channel on the bottom part of the gate in bulk FinFETs, the decreased junction leakage current due to blocking the vertical leakage path by PIOX layers, and the increased hot carrier lifetime can be applicable to future DRAM cell transistors.
Using a thin germanium interfacial passivation layer (IPL), for the first time we present surface channel n- and p-MOSFETs on GaAs substrate with TaN gate electrodes and HfO2 dielectric films. We used self-aligned and gate-last processes to fabricate MOSFETs on semi-insulating GaAs substrate. The electrical results from the buried channel and the surface channel-mode transistors are investigated....
A novel isolated LDMOS structure, using a simple yet effective concept of an asymmetric hetero-doped source/drain, is proposed. The asymmetric hetero-doped source/drain reduces the on-state resistance of the transistor due to the high n-type doping used for device drain drift, provides excellent ruggedness for parasitic NPN turned-on due to a minimized n+ source spacer, and also raises the device...
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