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The abnormal turnaround phenomenon of threshold voltage for the p-type low temperature poly-silicon thin film transistors (LTPS TFTs) stressed under a specific negative DC bias condition, which the gate voltage is about one half of the drain voltage, is investigated. There are two turnaround points for the TFT stressed with prolonged time. The sampling current of the TFT under the biasing stress is...
Poly-Si TFTs with vacuum cavities underneath the poly-Si gate edges (quasi-T gate poly-Si TFTs) were successfully realized by partially wet etching the gate oxide and encapsulating in a vacuum. Because of the vacuum cavity not only as an offset region to reduce the abnormal leakage current in the OFF-state but also as a field-induced drain (FID) to sustain the on-current in the ON-state, the electrical...
Poly-Si TFTs with vacuum cavity next to the gate-oxide edge (quasi T-gate TFTs) have been fabricated with the wet-etching of gate-oxide and in-situ vacuum encapsulation techniques. The device characteristics of the quasi T-gate TFTs are examined and better than those of conventional TFTs, resulting from the vacuum cavity as the offset region to reduce the leakage current and as the field-induced drain...
The instability characteristics of n-type low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) which are dynamically stressed in the OFF region with drain biased is investigated. Through the gate dynamically stressed in the OFF state with negative drain dc bias, the degradation mechanism of TFTs could be clarified and the defects are mainly generated in the source region. The...
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