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This paper presents a low power noise tolerant comparator design for arithmetic circuits. Instead of using domino logic, this paper uses a modified domino logic style. This logic uses semi-domino logic style and some extra footer transistors which lead to minimize power dissipation and noise of the comparator. The new comparator is compared with the basic domino comparator in terms of noise tolerance,...
The IEEE 802.11ac is the recently ratified standard developed for the fifth generation wireless fidelity technology, in which the multi-user (MU) multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) technique is adopted for the high data rate communication. In an MIMO-OFDM System, the forward/inverse fast Fourier transform (FFT/IFFT) processor is a key component. On...
This paper investigates the various aspects of network on Chip(NoC) design and its FPGA implementation. A parametric approach of evaluating the FPGA resources, delay and maximum frequency of operation for a NoC design has been described which may help the designer to take early decision related to NoC designing and prototyping. Virtual channel(VC), flit buffer depth and flit data width are taken as...
Scaling of CMOS technology improved the speed nevertheless the leakage currents are leftover as an adverse effect. The problem has taken a serious turn as the scaling extends into ultra-deep-submicron (UDSM) region. These unsolicited leakage currents should be minimized for the smooth functioning of the circuit. Designing of such leakage free nanoscale CMOS circuits turns to be a challenging task...
A significant amount of the total power in highly synchronous systems gets dissipated over clock networks. Therefore, low-power clocking schemes would be promising approaches for high performance designs. To reduce the power consumption and delay, a new flip-flop circuit technique has been designed in CMOS domino logic. These flip-flops are a class of dynamic circuit that can be interfaced with both...
Multiprocessor System-on-Chip platforms are gaining prominence in the field of SoC design, which accommodates several large heterogeneous semiconductor intellectual property (IP) blocks, integrated onto a single chip. However, there's a crisis of global interconnection with existing bus architectures in such SoC Designs. In response to this crisis, Network-on-Chip (NoC) is an upcoming paradigm, and...
A new low power dynamic CMOS one bit full adder cell is presented in this paper. In this design technique is based on semi-domino logic. This new adder cell was compared with some previous proposed widely used dynamic adders as well as other conventional architectures. Objective of this work is to inspect the power, delay, power-delay product and leakage performance of low voltage full adder cells...
Network on Chip (NoC) is a new paradigm to make the interconnections inside a System on Chip (SoC). By the developments achieved in integrated circuits (IC) manufacturing there have been attempts to design vast amounts of network on the chips in order to achieve more efficient and optimized chips. A better routing algorithm can enhance the performance of NoC. XY routing algorithm is a distributed...
This paper presents a new and efficient control scheme which adopted the voltage source inverter to decrease current harmonics generated by the nonlinear load. The sliding mode control is used in the current control loop to achieve fast dynamics and a simple proportional-integral controller is adopted in the outer voltage control loop to achieve slow dynamics. The proposed scheme implements simplified...
This paper describes a novel sliding mode method with the fuzzy controller approach in the development of unified power quality conditioner (UPQC) for reactive power, harmonics and both symmetric and asymmetric sag and swell compensation. The UPQC consists of both shunt and series converter having a common dc link. The shunt converter eliminates current harmonics generated from the nonlinear load...
Cryptographic implementation is one of the vital applications for FPGAs with security as its major standpoint. But it still requires a lot of efforts to keep it aloof from attacks like Side Channel Attacks (SCA). One of the major attacks that threaten the security of FPGA implementation of cryptographic algorithm is Differential Power Analysis (DPA). In this paper, we have discussed various approaches...
A new low power dynamic CMOS one bit full adder cell is presented. In this design technique is based on semi-domino logic. This new cell is compared with some previous proposed widely used dynamic adders as well as other conventional architectures. Objective of this work is to inspect the power, delay, power-delay-product and leakage performance of low voltage full adder cells in different CMOS logic...
VLSI circuit with higher performance and more functionality can cover wider cross-sections in applications. Designing such circuits requires additional peripherals and thus more nodes to be integrated with the mother circuit. Miniaturization of device channel length to sub-100nm dimension can allow high performance VLSI circuit design. However, such devices have a drawback of significantly higher...
This paper presents three different PLL based control algorithms for shunt active Power filter (SAPF) under the distorted supply condition. Different synchronisation techniques such as Modified SRF (MSRF-PLL), Transformation angle detector and SRF based PLL have been applied to SAPF and analyzed under different distortion conditions of supply voltage. From the simulation results, it is found that...
This paper presents the design of a low power and high performance circuit using a new CMOS domino logic family called feedthrough logic (FTL). Feedthrogh logic improves the performance of arithmetic circuit by performing partial evaluation in its computational block before its input signals are valid. FTL improves the speed of arithematic circuits along with more power consumption. The proposed modified...
With the technological advancements a large number of devices can be integrated into a single chip. So the communication between these devices becomes vital. The network on chip (NoC) is a technology used for such communication. A router is the fundamental component of a NoC. This paper focuses on the implementation and the verification of a five port router. The building blocks of the router are...
Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS...
In this paper a circuit design technique to reduce dynamic power consumption of a new CMOS domino logic family called feedthrogh logic is presented. The need for low power circuit with high speed has made it common practice to use feedthrough logic. The proposed modified circuit has very low dynamic power consumption compared to recently proposed circuit techniques for feedthrough logic styles. The...
This paper presents the design of a low power dynamic circuit using a new CMOS domino logic family called feedthrough logic. Dynamic logic circuits are more significant because of its faster speed and lesser transistor requirement as compared to static CMOS logic circuits. The proposed circuit has very low dynamic power consumption compared to the recently proposed circuit techniques for the dynamic...
Dynamic CMOS gates are widely exploited in high-performance designs because of their speed. However, they suffer from high noise sensitivity. The main reason for this is the sub-threshold leakage current flowing through the evaluation network. This problem becomes more and more severe with continuous scaling of the technology. A new circuit technique for increasing the noise tolerance of dynamic CMOS...
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