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Cloud Map-Reduce (CMR) is an advantage Map-Reduce platform and has been aroused more and more attention. To further balance the performance of job secluding among job cost, execution time and energy consumption, a locality-aware and energy-aware job pre-assignment algorithm is proposed for Map-Reduce of CMR in this paper. Firstly, the importance of rack in data locality and energy saving is analyzed...
Deduplication technology has been increasingly used to reduce the primary storage cost. In practice, it often causes additional on-disk fragmentation that impairs the reading performance. Existing deduplication algorithms mainly focus on the static data layout design so that the random I/O requests are largely avoided and the harmful effect can be alleviated. However, our trace-driven emulations show...
Integrating three-phase induction motor electromagnetic calculation program and multi-objective inverse optimization algorithm, a multi-objective & inverse three-phase induction motor optimization system with C++ is realized. This system can optimal design three-phase induction motor automatically. The design examples verify the effectiveness of the system.
This paper presents a method for designing two-channel hybrid filter banks by solving a minimax and a one-dimensional optimization problems derived from the near perfect reconstruction conditions. The design starts with a power-complementary structure of analog analysis filters with a free parameter. First, with this parameter fixed, digital synthesis filters can be designed in minimax sense by using...
Depth generation is the key technology in the 3DTV system. Due to the demands for accuracy and real-time execution, local methods are more suitable, but the challenge is to decide an appropriate window for each pixel. We propose a novel local method, which constructs the support windows adaptively only based on the intensity, and the process has no relation with disparities. This is the main difference...
SOC integrates an intact system on one single chip, so that the size of chip is dwindled. However, the difficulty and complexity of system circuit testing is increased. Kinds of constraint conditions should be considered in testing cores, in order to meet the high-performance requirements of circuit system test, including the realization of parallel module test with test power and priority constrains...
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