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A low-voltage circuit technology for 1.5-V, 64-Mb DRAMs designed to achieve a reasonable speed performance projected from existing trends is described. The DRAM has been deigned using novel low-voltage circuits. An RAS access time of 50 ns has been obtained with power dissipation as low as 44 mW. These results show that a low-voltage battery-operated DRAM is a promising target for the future
The technology used to fabricate high-speed and low-power 64-Mb DRAMs (dynamic random access memories) is described. The memory cell developed is a high-storage capacitance bit-line shielded stacked capacitor (STC) cell in which the storage capacitor is formed over the bit-line and a cylindrical storage node structure is used for low-voltage memory operation. The main features of the technology are...
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