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The authors report low-power, high-signal-to-noise-ratio (SNR) 16 Mbit DRAM (dynamic RAM) techniques which allow 1.5-V battery operation. To reduce power consumption, the data-line voltage swing is the sum of the threshold voltages for nMOS and pMOS transistors in the sense amplifier. A plate-pulse circuit technique, a three-level word pulse, and a 3.4- mu m/sup 2/ data-line shielded STC cell enhance...
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