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Alternatives for on-chip voltage limiters and direct sensing schemes were evaluated in terms of ease of design, voltage margins and speed. Based on these evaluations, a 0.3??m ECL 4Mb BiCMOS DRAM was designed with a simulated access time of 7.8ns. It incorporates a voltage limiter featuring connection to VCC terminals, a BiCMOS output stage and use of a band-gap reference scheme, and a direct sensing...
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