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Stress migration (SM) and electromigration (EM) are key reliability concerns for advanced metallization in nanoscale CMOS technologies. In this paper, the interaction between these two mechanisms is studied in dual-damascene Cu/low-k interconnects. It is found that these mechanisms are not independent; EM failure time could be strongly affected by the presence of residual stress induced by SM, causing...
Effect of backend interconnect critical dimension variation on IMD TDDB is studied. Statistical data shows that low-k dielectric TDDB time to failure correlates well with leakage current, which reflects actual trench-to-trench or trench-to-via spacing. So a lifetime projection method, based on equal electric field, is reported. A more realistic lifetime is achieved while predicting whole lot TDDB...
The effects of dielectric slots on Cu/Low-k interconnects reliability were studied. Dielectric slots were proven to be effective in suppressing stress-induced void failure but their impact on EM reliability was found to be minimal. Physical failure analysis and finite element simulations were used to explain the possible mechanisms associated to the different effects of dielectric slots on Cu/low-k...
The correlation of time-dependent dielectric breakdown (TDDB) reliability failure with scratches generated from chemical mechanical polishing (CMP) in 45 nm backend-ofline (BEOL) process is investigated and established. The wafer map of early TDDB failure samples matches well with the defect wafer map from bright field scans. Electrical fault isolation using thermally induced voltage alteration (TIVA)...
Auger depth profile analysis can be impeded by surface roughening during ion sputtering. This is especially noticeable when analyzing semiconductor devices because of the variety of materials that are susceptible to roughening, as well as the importance of very thin interfaces. A novel technique is presented in this article, which combines scanning Auger analysis with focused ion beam (FIB) thinning...
A high performance 45nm BEOL technology with proven reliability is presented. This BEOL has a hierarchical architecture with up to 10 wiring levels with 5 in PECVD SiCOH (k=3.0), and 3 in a newly-developed advanced PECVD ultralow-k (ULK) porous SiCOH (k=2.4). Led by extensive circuit performance estimates, the detrimental impact of scaling on BEOL parasitics was overcome by strategic introduction...
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