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We report a new nano-switching ESD protection mechanism and dual-polarity Cu/SixOyNz/W nano crossbar array ESD structures. Experiments show full ESD protection featuring fast response of 100pS ultra low leakage of <2pA and ESD protection of >9A. New dispersed local ESD tunneling model and CMOS integration are reported.
This paper presents design of an all-digital fully-integrated 5th-order Gaussian pulse generator (PG) for full band (3.1GHz-10.6GHz) impulse radio ultra wideband (IR-UWB) transceiver SoC. The design is implemented in a foundry 0.18μm CMOS process. New FCC effective isotropic radiated power (EIRP) aware design technique is used to optimize the PG. Measurement shows peak pulse amplitude of 533mV at...
This paper reports a single-chip full-band 3.1 10.6GHz ESD UWB LNA featuring cascode shunt-series feedback topology and very robust whole-chip ESD protection. Careful ESD+LNA co-design was excised to achieve full-chip circuit optimization with high ESD protection. This design is implemented in a foundry 0.18μm RFCMOS process. Measurement shows the highest reported ESD protection of 8.25kV, a peak...
A 3.1-4.8GHz LNA for lower-band UWB transceiver front-end ICs designed in a commercial 0.18μm CMOS is presented. The LNA features current reuse, resistive feedback, complete and robust full-chip ESD protection. LNA circuits with and without ESD protection are compared to minimize ESD-induced LNA performance degradation. Experiment shows a gain of 13.2dB, excellent input reflection of -13.4dB, NF of...
This paper reviews key factors to practical ESD protection design for RF and analog/mixed-signal (AMS) ICs, including general challenges emerging, ESD-RFIC interactions, RF ESD design optimization and prediction, RF ESD design characterization, ESD-RFIC co-design technique, etc. Practical design examples are discussed. It means to provide a systematic and practical design flow for whole-chip ESD protection...
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