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Vertical double gate floating body (FB) Z-RAM memory cell technology fabricated on a recess gate DRAM technology is presented. Cell operating voltage of 0.5V with comparable static retention and > 1000× improvement in dynamic retention is reported. The reported vertical double gate FB cell is the cell with the lowest operation voltage reported to date.
The operating characteristics and retention times of floating body cells and arrays using Z-RAMreg technology fabricated on a 50 nm DRAM process are presented. For the first time, data retention time longer than 8 s at 93degC and 1.6 V wide programming window are obtained on floating body cells as small as 54 nm times 54 nm. These results demonstrate the suitability of floating body memories for DRAM...
In this work, a new efficient simulation method with comprehensive physical models is developed to evaluate the performance of CTM at various biases, temperatures, and gate stack configurations. The dominant physical mechanisms on the P/E/R operations of CTM are clarified.
The effects of local accumulated free carriers on CTM cell's performance are investigated by numerical simulation. Simulation results indicates that local accumulated free carriers do not affect programming and erasing characteristic, however, they are important to CTM's retention characteristic, especially in low threshold state. For CTM cell with thick tunneling oxide and shallow trap depth in charge...
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