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In this paper we describe our approach towards highly configurable neuromorphic hardware systems that serve as useful and flexible tools in modeling neuroscience. We utilize a mixed-signal VLSI model that implements a massively accelerated network of spiking neurons, and we describe a novel methodological framework that allows to exploit both the speed and the programmability of this device for the...
We will set up a fully functional system consisting of a custom design hardware framework (Figures 1 and 2) with the neural network chips described in the appended 4-page paper, Section II-A. The framework is connected digitally to a host PC, on which we will run a software that provides the simulator-like, flexible and non-expert usability of the neuromorphic device as described in the appended paper,...
This paper presents a network architecture to interconnect VLSI neural network chips to build a distributed ANN system. The architecture combines techniques from circuit switching and packet switching to provide two different service classes: isochronous connections and best-effort packet transfers. The isochronous connections are able to transport the axonal data of artificial neurons between VLSI...
When studying the different aspects of synaptic plasticity, the timescales involved range from milliseconds to hours, thus covering at least seven orders of magnitude. To make this temporal dynamic range accessible to the experimentalist, we have developed a highly accelerated analog VLSI model of leaky integrate and fire neurons. It incorporates fast and slow synaptic facilitation and depression...
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