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During 2006 and spring 2007, integration and commissioning of trigger and data acquisition (TDAQ) equipment in the ATLAS experimental area has progressed. Much of the work has focused on a final prototype setup consisting of around eighty computers representing a subset of the full TDAQ system. There have been a series of technical runs using this setup. Various tests have been run including ones...
The ATLAS trigger and data acquisition system has been designed to use more than 2000 CPUs. During the current development stage it is crucial to test the system on a number of CPUs of similar scale. A dedicated farm of this size is difficult to find, and can only be made available for short periods. On the other hand many large farms have become available recently as part of computing grids, leading...
The ATLAS experiment at the Large Hadron Collider (LHC) will face the challenge of efficiently selecting interesting candidate events in pp collisions at 14 TeV center-of-mass energy, whilst rejecting the enormous number of background events. The high-level trigger (HLT = second level trigger and event filter), which is a software based trigger will need to reduce the level-1 output rate of ap 75...
The ATLAS combined test beam in the second half of 2004 saw the first deployment of the ATLAS high-level triggers (HLT). The next steps are deployment on the pre-series farms in the experimental area during 2005, commissioning and cosmics tests in 2006 and collisions in 2007. This paper reviews the experience gained in the test beam, describes the current status and discusses the further enhancements...
ATLAS is one of the four LHC experiments that will start data taking in 2007, designed to cover a wide range of physics topics. The ATLAS trigger system has to cope with a rate of 40 MHz and 23 interactions per bunch crossing. It is divided in three different levels. The first one (hardware based) provides a signature that is confirmed by the following trigger levels (software based) by running a...
The ATLAS trigger system is composed of three levels: an initial hardware trigger level (LVL1) followed by two software-based stages (LVL2 trigger and event filter) included in the high level trigger (HLT) and implemented on processor farms. The LVL2 trigger starts from LVL1 information concerning pointers to restricted so-called regions of interest (ROI) and performs event selection by means of optimized...
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