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We demonstrate multi-VT engineering on both CMOS bulk and FinFET devices through As implantation into a 1.0nm EOT TiN/high-K gate stack within a single metal single dielectric approach. We determine a As implantation process window enabling VT tuning without any device degradation. It is shown that this approach is suitable for multi-VT engineering with aggressively scaled dielectrics and, particularly,...
Source/drain formation in ultra-thin body devices by conventional ion implantation is analyzed using atomistic simulation. Dopant retention is dramatically reduced by backscattering for low-energy and low-tilt angles, and by transmission for high angles. For the first time, molecular dynamics and kinetic Monte Carlo simulations, encompassing the entire Si body, are applied in order to predict damage...
Scaling the fin width in fully-depleted FinFETs can improve short channel effect control, but may be accompanied by a on-state drive current degradation. Ion implantation is a leading candidate as the means to introduce dopants into the silicon, but is often accompanied by amorphization when highly doped source-drain regions are formed. Thin-body silicon recrystallization after amorphization is not...
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