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We present an open source stack for the development of custom FPGA boards, primarily but not limited to PCI Express interconnects. Supporting current Linux distributions, the stack consists of a PCI driver, an IP core for a DMA engine, a hardware abstraction library for IO operations, and a buffer management library for efficient handling of data transfers between an application and a FPGA design...
An additional inner layer for the existing ATLAS Pixel Detector, called Insertable B-Layer (IBL), is under design and it will be installed by Phase I. New front-end readout ASICs fabrication (FE-I4) will replace the previous chips in this layer. The new system features higher readout speed - 160Mb/s per ASIC - and simplified control. The current data acquisition chains are composed of front-end and...
The detectors of the CBM experiment, under construction at GSI, Germany, will generate an enormous data flow of 1TB/s, which is provided via approximately 6000 optical links to the DAQ system. For proper analysis, so called events have to be composed of data packets originating from different geometrical regions and with temporal coincidence, at a resolution of 1 nS. Routing and aggregating of packets...
The active buffer project is part of the CBM (compressed baryonic matter) experiment and takes advantage of the DPR (dynamic partial reconfiguration) technology, in which a dynamic module can be reconfigured while the static part and other dynamic modules keep running untouched. Due to DPR, design flexibility and simplicity are achieved at the same time. The correctness and the performance have been...
This paper presents a framework for rapid development of FPGA based custom processors based on floating-point calculation units. The framework consists of a fully parameterized floating-point library, an easy-to-use pipeline generator and an interface generator for memory and I/O-modules. The performance of this approach is shown for the implementation of an SPH-algorithm.
In the last years, FPGAs became capable of performing complex floating-point based calculations. For many applications, highly parallel calculation units can be implemented which deliver a better performance than general-purpose processors. This paper focuses on applications where the calculations can be done in a pipeline, as it is often the case for simulations. A framework for rapid design of such...
This paper presents the FPGA development system CHDL. The project was started to implement new methods of hardware software cosimulation and to integrate special FPGA features like the readback functionality for hardware debugging purposes. Many existing tools do not have such support or they put the main emphasis on either synthesis or simulation. In the CHDL system synthesis and simulation are both...
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