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The present paper describes the development of high voltage CMOS process line-up (5/11/20/30V) for display driver applications, based on 0.13mum CMOS process with aluminum metallization. The advantages are smaller size of SRAM bit cell and lower process cost. High voltage CMOS devices, 1.5V(LV) logic CMOS, 5.5V(MV)CMOS, poly-Si resistor (HR/MR), MOS-capacitor, SRAM and OTP are available. 10.8mum device...
The process integration schemes for CMOS FinFET fabricated on bulk Si substrate are discussed from the viewpoints of device size scalability and short channel effect control. The trimming technique by special oxidation was applied to reduce fin width down to sub-10 nm regime. A novel punch through stopper (PTS) formation process was introduced to the bottom of the channel region to scale the gate...
Our newly developed neutral beam (NB) etching accomplished the damage-free (defect-free and smooth surface) fabrication of high aspect rectangular Si-fins for the first time. The fabricated FinFETs realized higher device performance (higher electron mobility) than that using a conventional reactive ion etching. The improved mobility is well explained by the NB etched atomically-flat surface. Our new...
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