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Lead-free reflow soldering techniques applying AuSn as well as SnAg electroplated bumps were chosen for the evaluation of the flip-chip-bonding process for X-ray pixel detectors. Both solders can be used in pick-and-place processes with a subsequent batch reflow suitable for high-volume production. AuSn solder was selected because of its fluxless bondability, good wettability, and self-alignment process...
Most of the wafer level 3-D technologies are using Through-Silicon Vias (TSV). The main barriers for these approaches are high cost, issues with electrical isolation within the Si via and the need of high investments for new equipment which is not used in WLP up to now. A planar integration technology of ultra-thin bare dice in a Wafer-Level Thin Film technology yield to a high-dense module will be...
Heterogeneous integration bridges the gap between nanoelectronics and its derived applications. Currently MEMS and their signal conditioning ASICs are produced and packaged at different industry sectors (different fabs). To reduce costs and enhance yield and performance at the same time this quite expensive way of packaging has to be modified. This paper presents a different packaging concept. It...
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