A switched-capacitor delay circuit that is offset-compensated and insensitive to stray capacitance and to capacitor mismatch is proposed. It uses a four-phase clock and contains a single operational amplifier, two capacitors and seven switches. A delay line composed of such building blocks requires only two operational amplifiers per three delay sections and two clock phases per sample.<<ETX>>
A direct by-inspection method for the derivation of signal-flow graphs (SFGs) for multiphase stray-insensitive switched-capacitor (SC) networks is presented. Compared to this method, others are relatively complicated and not direct in the sense that they require intermediate steps. The multiphase analysis presented in the paper is a generalisation of the method shown previously (see A. Dabrowski,...
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