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A low-jitter fractional spread-spectrum clock generator (SSCG) by utilizing a fast-settling dual charge-pump (CP) technique has been developed for Serial-ATA (SATA) applications. The proposed fast-settling dual CP technique not only reduced a design area but also shortened settling-time by controlling the CP operation sequence in an SSCG settling period. A multi-modulus divider using differential...
A serial ATA PHY was fabricated in a 0.15-mum CMOS process with a technique of calibrating a spread spectrum clock generator (SSCG). This technique involves calibrating the SSCG output signal frequency, which does not meet the serial-ATA specifications due to large variations in the reference oscillator, by utilizing the received signal during a power-on sequence. This is achieved by shifting the...
A voltage-controlled oscillator (VCO) for optical-disc-drive (ODD) applications was developed. This VCO selects the most appropriate current-controlled oscillator (CCO) from three CCOs in order to satisfy various ODD read/write speeds. It produces the frequency characteristics of a maximum frequency limiter in order to prevent unlocking of a PLL. Moreover, the VCO applies a trimming method to correct...
Implemented in a 0.15/spl mu/m CMOS process, the spread-spectrum clock generator uses the fractional PLL controlled by a /spl Delta//spl Sigma/ modulator An adaptive level shifter is adopted for expanding the input range of the /spl Delta//spl Sigma/ modulator. The 1.5GHz prototype achieves the peak spurious reduction level of 20.3dB and the random jitter of 8.1 ps in a 250-cycle averaging period.
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