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A low jitter voltage-controlled oscillator (VCO) with high-frequency-limiter and an auto-calibration technique suitable for this VCO was developed for a spread-spectrum clock generator (SSCG). The high-frequency-limiter prevents the SSCG from going into an unlocked state. The proposed VCO achieved far less jitter than a conventional one because a proposed structure has less operating MOSs. The auto-calibration...
Implemented in a 0.15/spl mu/m CMOS process, the spread-spectrum clock generator uses the fractional PLL controlled by a /spl Delta//spl Sigma/ modulator An adaptive level shifter is adopted for expanding the input range of the /spl Delta//spl Sigma/ modulator. The 1.5GHz prototype achieves the peak spurious reduction level of 20.3dB and the random jitter of 8.1 ps in a 250-cycle averaging period.
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