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In this paper, a wide range and low power multi-rate receiver for DisplayPort Version 1.3 is proposed. In order to extend the bandwidth, a high speed AC coupled interconnect receiver comprising output compensated negative impedance and positive feedback techniques is introduced. Furthermore, the automatic bit-rate tracking scheme is used for clock and data recovery (CDR) to achieve wide data rate...
An all-digital delay-locked loop (ADDLL) is proposed for wide range, fast lock, low jitter and high process-voltage-temperature (PVT) tolerance. The proposed phase tracking generator (PTG) produces two tracking rising and falling phases in only 2 cycles for fast lock and wide-range. The digital phase interpolator (DPI) and the control block are adopted to calibrate the phase offsets and random jitters...
In this paper, a line driver for HomePlug AV powerline communication system has been described. The proposed line driver includes a damping factor control (DFC) network which suppressed the open loop high frequency peaking effect to improve the stability for the various characteristic impedance of powerline. The line driver was fabricated in TSMC 0.18-μm CMOS technology and occupied 0.195 mm2 active...
A 10-bit current-steering digital-to-analog converter (DAC) has been proposed. This study is used for the transmitter (Tx) of the powerline communication (PLC) analog-front-end (AFE), and it reaches the standard of the HomePlug AV2. The proposed DAC also uses a technique as digital random-return-to-zero (DRRZ) [1] to achieve high performance in the OFDM communication systems. The test chip was fabricated...
Delay-locked loops (DLLs) are widely adopted for clock generation and synchronization in high performance digital systems. The design of analog DLLs has become a challenge due to the trends associated with CMOS scaling, namely, high leakage current, low supply voltage, etc. Consequently, many designers have shifted their focus to digitally-assisted or all-digitally implemented DLLs, which are easier...
A differential AC coupled transceiver for high-speed and low-swing has been implemented in a 0.18µm CMOS process. The proposed architecture includes a pulse receiver and a broadband limiting amplifier to recover a NRZ signal from a 75fF capacitive coupled channel. The system works at 12Gb/s through 10cm FR4 printed circuit board interconnect, while dissipating only 13.5mW with a bit error rate less...
The chaotic UWB RF transceiver system is designed in CMOS 0.18 m technology with flexible chaotic signal generation. Although the chaotic UWB technology is expected as a promising solution for near-range connectivity services, it has a limitation for commercial applications due to a fixed-band chaotic signal generator. In this paper, the noble flexible chaotic signal generator with adjustable frequency...
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