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For next-generation memory and logic devices, there have been suggested many concepts of the unidirectional coherent motion of magnetic domain walls (DWs) [1-3]. Such motion occurs either by injecting large electric currents into nanowires [1] or by employing DW tension induced by sophisticated structural modulation [2, 3]. These schemes, however, require either a high threshold [1] or highly sophisticated...
In real-world law enforcement encounters, a seemingly docile situation can turn violent in a matter of seconds. Being able to identify the signs of imminent aggression or violence may be extremely important in keeping safe those in harm's way. In the current study university student observers were shown an array of 12 facial expressions that included target images for two types of assault - premeditated...
A 1.35 ns random access and 1.7 ns-random-cycle SOI embedded-DRAM macro has been developed for the POWER7™ high-performance microprocessor. The macro employs a 6 transistor micro sense-amplifier architecture with extended precharge scheme to enhance the sensing margin for product quality. The detailed study shows a 67% bit-line power reduction with only 1.7% area overhead, while improving a read zero...
This paper presents a 1.7 ns-random-cycle SOI embedded-DRAM macro developed for the POWER7?? high-performance microprocessor and introduces enhancements to the micro-sense-amplifier (??SA) architecture. The macro enables a 32 MB on-chip L3 cache, eliminating delay, area and power from the off-chip interface.
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