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In this paper, we introduce binary-weighted digital control into the gain cell design of a distributed transversal filter (DTF) to demonstrate the benefits of digitally-assisted RF circuits. By effectively integrating a digital-to-analog converter (DAC) into the gain cell, the new design can improve gain cell's linearity and hence DTF's dynamic range. A 5-tap DTF prototype was designed and implemented...
The stringent emission mask and interference specifications in ultra-wideband (UWB) impulse radios present great challenges for the transceiver architecture design and circuit implementation. This paper proposes to use integrated distributed transversal filters (DTF) for pulse shaping in the transmitter and for narrow-band interference (NBI) suppression in the receiver. Analyses show that an integrated...
We propose a new GHz clock distribution scheme, injection-locked clocking (ILC). This new scheme uses injection-locked oscillators as the local clock regenerators. It can achieve better power efficiency and jitter performance than conventional buffered trees with the additional benefit of built-in deskewing. A test chip is implemented in a standard 0.18mum digital CMOS technology. It has four divide-by-2...
A low power LVDS driver embedded in ADC system is presented. A new current mirror circuit is used to guarantee the matching between the top and bottom current sources. The current flowing through the termination resistors can be controlled by an off-chip resistor. By combining the design concepts of prior arts, the driver is fabricated in a 0.18mum 1.8V CMOS process. The simulated results show that...
A new injection-locked frequency divider (ILFD) topology is proposed for divide-by-odd-number operation. An 18 GHz divide-by-3 prototype is implemented using 0.18mum standard digital CMOS with low-resistivity substrate. It achieves 1 GHz locking range with 3.4dBm injection power, which increases to 3.2GHz with built-in tuning. The phase noise is close to theoretical value of 9.5dB down from input
We present an injection-locked divider (ILFD) with a double-balanced structure to generate two signals with tunable phase difference. A circuit prototype was designed and fabricated using a standard 0.18mum digital CMOS technology, and generates dual-phase signals at 4.8-6 GHz. The phase difference of the two output signals can be tuned independently by 55deg, and differentially by 100deg, both centered...
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