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A 4+2T SRAM is proposed that offers searching and logic functions. The cell uses the N-well as the write wordline (WL) and eliminates the access transistors. Decoupled read paths enable reliable multi-word activation for in-memory Boolean logic functions. The SRAM can reconfigure to BCAM/TCAM for searching operations, with 0.13fJ/search/bit at 0.35V. Forty test chips in 55nm deeply depleted channel...
A spin synapse with analog programmability using all charge current is proposed. Compared with using spin current, the proposed all-charge-current synapses can be placed in a larger cross-bar array to form a denser and larger neural network. Using the current summation, DOT product can be realized. We further employ a compact racetrack converter as the neuron to implement a rectified-linear neural...
Physically Unclonable Functions (PUFs) are among the most promising security primitives for low cost solutions of key storage, chip authentication, and supply chain protection. Two types of PUFs exist in literature [1–6], a “strong” PUF with a large challenge-response space [6] and a “weak” PUF providing a limited length key (chip ID) [1–5]. While the former provides better security theoretically,...
Size of STI wells is another significant factor to affect the stress magnitude (device mobility) besides size of transistor active regions. In this paper, we present a technique for improving device mobility in the critical path via global STI well width adjusting following the chip placement stage. The methodology formulates the original device mobility enhancement problem as a series of convex geometric...
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