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Although Moore's law is slowing down, design productivity is still a big issue in semiconductor industry. Drivers are the trend to 3D integration, the addition of design goals such as ultra-low power and safety, and an increasing number of designs in IoT and automotive areas. EDA tools such as high-level synthesis cover a small design area only. Also, the impact of IP reuse is overestimated since...
Although the Moore's law is slowing down in terms of technology node scaling, researchers are inventing new methods to keep the design productivity on the rising trend. As a consequence, the complexity of hardware designs will continue to grow, which results in further hardening of functional verification. Assertion based verification is well established and proven to be an effective RTL verification...
This paper gives a snapshot on the current activities in the Accellera SystemVerilog standardization. Needs and requirements from the user’s side are covered as well as major new concepts and current status of the standardization and of available tools. The paper also gives links to papers currently available on the web.
Today's dominant RTL languages, VHDL and (System) Verilog, were designed as description and simulation languages. Therefore, they have a clearly defined - but not in all cases deterministic - simulation algorithm as backbone of the language definition. Both languages have been adopted as RTL design languages but still impose a lot of simulation/synthesis mismatches. As a further disadvantage, considerable...
Evaluating the outcome of analog simulations is a common, mostly manually carried out task in the pre-silicon verification process of mixed-signal ICs. Its non-automated nature makes it an error-prone and time-consuming procedure. For this very reason, we introduce a novel approach for performing this evaluation automatically resulting in significantly reduced turnaround times as well as a considerably...
Circuit robustness can be increased with selective Flip-Flop hardening. Finding candidate sets of Flip-Flops for optimal selective hardening requires costly fault simulations, in particular if we consider safety properties stating that a bad state should never be reached in future. We present a fully symbolic formal method that gives a rigorous robustness measure without the need of extensive fault...
The need for safer and more robust hardware systems increased considerably in the automotive industry after the introduction of the safety standard ISO 26262. As a result, fault injection became a major verification milestone for safety-critical applications. However, safety-verification methods for gate level (GL) and RTL models suffer from long simulation time and large fault-injection campaigns...
Several leading research groups name hardware generation as the next disruptive productivity improvement after IP-reuse. Metamodeling and code generation have already demonstrated a speedup by a factor 3× for the complete implementation phase of a chip. Furthermore, code size reduction by a factor of 3× was achieved with the hardware generation language (HGL) Chisel.
Safety-critical systems-on-chip currently undergo extensive fault-effect analyses. To meet the safety requirements of ISO 26262, most frequently fault-injection campaigns are per- formed. Due to the exponentially growing fault-verification space, faster simulation possibilities than enabled by register transfer (RT) and gate-level (GL) models are under investigation. Fault injection on virtual prototypes...
The verification complexity of safety-critical systems on chip increased manifold after the introduction of ISO 26262, the safety standard for automotive applications. As a result, checkpoint-restore techniques have been implemented to speed-up fault-injection simulations of register-transfer level and gate-level models. However, these techniques are not suitable for safety verification, since they...
In this paper, we apply model-driven techniques to create a link between bottom-up and top-down safety analysis methods. Around MetaFPA, an internal framework for Metamodeling-based Failure Propagation Analysis, we build a safety evaluation environment integrating standard tools used for FMEDA: Failure Modes, Effects, and Diagnostic Analysis (e.g., Excel spreadsheets) and FTA: Fault Tree Analysis...
Rapidly rising system complexity has created a growing productivity gap in the design of electronic systems. One critical component is Hardware-dependent Software (HdS), the importance of which is often underestimated. In this chapter, we introduce HdS and illustrate its role in the overall system design context. We also provide a brief overview and define a basic HdS terminology and conclude with...
This chapter addresses HW/SW interface implementation and modeling. As introduction, basic concepts regarding HW/SW interfaces on both HW and SW side are presented in detail. The focus is on several aspects of register and bit field read/write access, address mismatch, synchronization, and data alignment. The HW micro-architecture is outlined in block diagrams, the SW code is listed in C-code snippets...
Hardware-dependent Software (HdS) plays a key role in desktop computers and servers for many years. Mainly due to its flexibility, the possibility of late change, and the quick adaptability, the relevance of HdS in the domains of embedded systems and in Systems-on-Chip (SoCs) has significantly increased.Despite its importance, the role of HdS is most often underestimated and the topic is not well...
This paper gives a snapshot on the current activities in the Accellera SystemVerilog standardization. Needs and requirements from the user’s side are covered as well as major new concepts and current status of the standardization and of available tools. The paper also gives links to papers currently available on the web.
Formal techniques seem to be a way to cope with the exploding complexity of functional safety analysis. Here, the overall fault propagation probability to a certain safety-point in the design must be analyzed. As a consequence, the careful verification of the design is no longer sufficient. In addition, the propagation of all possible faults potentially showing up at all of the design's internal nodes...
Virtual Prototypes (VPs) have been now widely adopted by industry as platforms for early SW development, HW/SW co-verification, performance analysis and architecture exploration. Yet, rising design complexity, the need to test an increasing amount of software functionality as well as the verification of timing properties pose a growing challenge in the application of VPs. New approaches overcome the...
Certifying an electrical/electronic system as functionally safe requires a range of analysis and assessment procedures, which must be performed during the different design and manufacturing phases. In the automotive context, the ISO 26262 standard prescribes a set of methods, including FMEDA (Failure Modes, Effects, and Diagnostic Analysis), to evaluate the safety integrity level of the product. FMEDA...
This paper presents an industry proven Metamodeling based approach to System-Level-Synthesis which is seen as generic design automation strategy above today's implementation levels RTL (for digital) and Schematic Entry (for analog). The approach follows a new synthesis paradigm: The designer develops a simple domain and/or design specific language and a smart tool synthesizing implementation level...
Designing Automotive SoCs requires product specific support of one or more different design targets as different degrees of safety, reliability, very low power, or high current support as well as different design features as multi-core, sensor-on-chip, or system-in-package. Considering that wide design space, it's clear that EDA industry that is focusing on generic applicable tools leaves a wide field...
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