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The objective of the hArtes (holistic approach to reconfigurable real time embedded systems) is to provide a tool set that facilitates the management of entire design flow. Despite of its improved design productivity, the two bottleneck are: (1) capturing initial application specifications in the specified graphical tool and (2) Cycle accurate performance estimation in design space exploration. We...
The hArtes -holistic approach to reconfigurable real time embedded systems- design flow addresses the development of an holistic tool-chain for reconfigurable heterogeneous platforms. The entire tool-chain consists of three phases: algorithm exploration and translation, design space exploration and system synthesis. This paper evaluates the tools in the design space exploration phase and the system...
This third-generation Chip-Multithreading (CMT) SPARC processor consists of 16 cores with shared memory architecture and supports a total of 32 main threads plus 32 scout threads. It is targeted for high-performance servers, and is optimized for both single- and multi-threaded applications. The 396 mm2 chip is fabricated in an 11 metal layer 65-nm CMOS process and operates at a nominal frequency of...
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