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This paper presents a new pipeline architecture for low-power and high-speed digital adaptive equalizer. The proposed architecture achieves enhancement in terms of speed and power consumption by sharing the input delay stage with input data multiplication and by scaling down the supply voltage. The adaptive equalizer for PRML disk-drive read channels adopting the proposed pipeline architecture is...
This paper describes a new pass-transistor logic family, named PPL(Push-pull Pass transistor Logic), for low voltage and low power which restores outputs by the push-pull operation. Using PPL circuits, 40-stage full adder chain and 8-bit multiplier are designed and fabricated in a 0.8??m CMOS process technology. PPL achieves 36.4ns delay with the power consumption of 0.45mW/100MHz in the full adder...
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