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Test point insertion methods to reduce the number of test patterns at register transfer level are required for the adaptability of traditional VLSI design flows and the reduction of time to search test point locations. In this paper, we propose a design-for-testability method at register transfer level to enable operational units as many as possible to be concurrently tested in scan testing. Using...
Fault diagnosis methods for specified fault models might deduce wrong faults as suspicious candidate faults (misprediction). The methods might not be able to also deduce suspicious candidate faults (non-prediction). In this paper, a fault diagnosis method for a single universal logical fault model in scan testing is proposed. In the fault diagnosis method, a diagnostic fault simulation for a single...
Recently, the increased utilization of outsourcing services for a part of designing VLSIs might reduce the reliability of VLSIs. There is a risk that hardware Trojan circuits are inserted into VLSIs by attackers at design phases. It is difficult to detect Trojan circuits by functional verification and testing. In this paper, we propose a hardware Trojan circuit detection method based on a pair of...
A binding method for hierarchical testability has been proposed to increase the number of testable operational units in hierarchical testing using behavioral level circuits [2]. The method aims to synthesize many operational units which can be tested by generated test sequences using hierarchical test generation. In this paper, we propose a scheduling method for hierarchical testability to increase...
In recent years, various high-level test synthesis methods for data paths have been proposed for the improvement in design productivity and test cost reduction. Most of the approaches assume that controllers and data paths are isolated from each other, and hence the hardware overhead becomes large. On the other hand, the approach without separation of a controller and a data path usually decreases...
High power dissipation can occur by high launch-induced switching activity when the response to a test pattern is captured by flip-flops (FFs) in at-speed scan testing, resulting in excessive IR drop. IR drop may cause significant capture-induced yield loss in the deep-submicron era. It is known that test modification methods using X-identification and X-filling are effective to reduce power dissipation...
In this paper, we propose a new low capture power test generation method based on fault simulation to reduce the number of unsafe faults. The method uses capture-safe test vectors in an initial test set to generate new test vectors. Our experimental results show that the use of this method reduces the number of unsafe faults by 94% on average, and while requiring less test generation time compared...
The increased utilization of outsourcing services for designing and manufacturing LSIs can reduce the reliability of LSIs. Trojan circuits are malicious circuits that can leak secret information. In this paper, we propose a Trojan circuit whose detection is difficult in AES circuits. To make it difficult to detect the proposed Trojan circuit, we propose two methods. In one method, one of test mode...
In this paper, a don't care (X) identification method for test compaction is proposed to reduce the number of test patterns. An X-identification method identifies many X inputs of test patterns in a given test set. However, conventional X-identification methods may be less effective for application-specific fields such as test compaction since the X-bits concentrate on particular primary inputs. The...
Overtesting induces unnecessary yield loss of VLSIs. Untestable faults, which have no effect on the normal functions of circuits, may be detected in scan testing through scan chains. In this case, the detected untestable faults cause overtesting. Untestable faults consist of uncontrollable faults, unobservable faults, and uncontrollable and unobservable faults. Uncontrollable faults may be detected...
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