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Compact model is not only a tool for IC design but also the unique bridge between IC manufacturing and design. It needs not only a mathematical model of a prototype transistor but also accurate models of many real device effects of the modern transistor. Compact model can address not only circuit performance but also reliability. BSIM and BERT are used as examples.
MOSFET gate oxide scaling limits are examined with respect to time-dependent breakdown, defects, plasma process damage, mobility degradation, poly-gate depletion, inversion layer thickness, tunneling leakage, charge trapping, and gate delay. It is projected that the operating field will stay around 5 MV/cm for reliability and optimum speed. Tunneling leakage prevents scaling below 2 nm, which is sufficient...
Electromigration reliability of different metallization systems and structures under bidirectional current stress is studied in a wide frequency range (from mHz to 200 MHz). The experimental results show that at very low frequencies, the damage healing factor and lifetime under AC stress increases with increasing frequency. At high frequencies, the pure AC lifetime was found to be determined by the...
This paper investigates the physics of voltage and temperature accelerated breakdown testing of silicon dioxide within the framework of an anode hole injection model which can predict low voltage (3.3 V and below) breakdown lifetime. The field acceleration rate is shown to be independent of temperature, while the reduction of oxide breakdown lifetime at increased temperature is due to the oxide's...
ESD protection capability of SOI CMOS output buffers has been studied with human body model (HBM) stresses of both positive and negative polarity. Experimental results show that the ESD discharge current is absorbed by the NMOSFET alone. Unlike bulk technologies where the bi-directional ESD failure voltages are limited by positive polarity stresses, SOI circuits display a more serious reliability...
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