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Record 9nm half-pitch functional Transition-Metal-Oxide based Resistive Random Access Memory (TMORRAM) cell and the lowest reported 1μA programming current (Iprog, both Set and Reset) have been achieved with thermally oxidized sub-stoichiometric WOx and Nano Injection Lithography (NIL) technique. The unexpectedly low programming current at 9nm diameter has been examined in-depth, it offers potential...
A new tunneling transistor structure is introduced that offers several advantages over prior designs. Notably, tunneling area is substantially increased. Turn on/off swing is improved by engineering doping profile to ensure tunneling initiates in high electric field region. TCAD simulations explore the critical design considerations. The concept of heterojunction tunneling is introduced as a means...
Growing IC power use poses challenges for thermal management and electricity conservation. A low voltage green transistor could be the key to allowing more growth of microelectronics.
A novel transistor design which utilizes positive feedback to achieve steep switching behavior is proposed and demonstrated. The feedback (FB) FET exhibits very low subthreshold swing (~2 mV/dec) and high ION/IOFF ratio (~108) to allow for significant reductions in gate voltage swing (to below 0.5V). It is a new candidate to replace the MOSFET for future low-power electronic devices.
IC power consumption is not only a package thermal issue but also a significant and fast growing part of the world electricity consumption. A new low voltage transistor could contribute greatly to the need for a new Vdd scaling scenario. Green transistor (gFET) is based on tunneling and provides Ion and Ioff far superior to MOSFET at 0.2V if suitable low-Eg material is introduced into IC manufacturing.
A novel hetero-tunnel transistor (HtFET) with a heterostructure parallel to the dielectric interface is proposed for low-voltage (low-power) electronics. Its potential of scaling Vdd down to 0.2 V is examined with quantum mechanical tunneling theory. Data from high-K metal-gate, Si on Ge hetero-tunnel transistor verifies the HtFET concept.
A novel hetero-tunnel transistor (HtFET) with a heterostructure and ultra shallow junction parallel to the dielectric interface is proposed for low-voltage (low-power) electronics. Its potential of scaling Vdd down to 0.2 V is examined with quantum mechanical tunneling theory. Data from high-K metal-gate, Si on Ge hetero-tunnel transistor verifies the HtFET concept.
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