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The high current and ESD effects on VLSI interconnect metallization have been characterized and a model for heating under ESD conditions is presented. It is shown that thermal breakdown occurs when the resistances increase by a factor of >3.6 due to melting of metal lines. After the metal is molten, the thermal stress is required to exceed the fracture strength of the oxide/nitride layers in order...
ESD protection capability of SOI CMOS output buffers has been studied with human body model (HBM) stresses of both positive and negative polarity. Experimental results show that the ESD discharge current is absorbed by the NMOSFET alone. Unlike bulk technologies where the bi-directional ESD failure voltages are limited by positive polarity stresses, SOI circuits display a more serious reliability...
Using RAD, a new module of Berkeley Reliability Tools (BERT), as a tool, users can design circuits to be radiation hard and characterize circuit behavior in environments where radiation is present. Previous simulators could not provide circuit output waveforms after radiation because it was difficult to simulate the effect of radiation on a circuit in operation (AC bias condition) and because radiation...
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