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This paper presents a high dynamic range (DR) linear-logarithmic (Lin-Log) CMOS image sensor (CIS) pixel with threshold voltage cancellation technique for pixel fixed pattern noise (PFPN) reduction. A tunable pixel response curve was applied for different environments. To avoid the gain loss of source follower in conventional APS structure, a column shared-amplifier with programmable gain was also...
This paper presents a high dynamic range (DR) linear-logarithmic (Lin-Log) CMOS image sensor (CIS) pixel with on-chip tunable linear range and threshold voltage cancellation scheme for reducing fix pattern noise (FPN). A column shared-OP with programmable gain was also applied to reduce the gain loss of source follower in conventional APS structure. A prototype chip with 100 × 100 pixel array and...
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