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SPlCE-compatible modeling with generalized lumped devices is used to simulate the spatial and time dependence of photogenerated carriers with standard circuit simulators. Equivalent voltages and currents are used in place of minority carrier excess concentrations and minority carrier currents respectively. The initial light-induced excess carrier concentration in silicon is accounted by means of distributed...
This work reports the results of a layout-aware substrate modeling methodology for HVCMOS technologies. The model relies on the extraction of parasitic substrate network to simulate with circuit software parasitic lateral NPN bipolar transistors with multi-collector configuration. This allows to predict and analyze the injected substrate currents distribution through the chip and to explore different...
Ultra-Thin Body and Box (UTBB) Fully-depleted Silicon-on-Insulator (FDSOI) MOSFETs exhibit very high transit frequency granting advantageous RF and low-power circuits design. This requires accurate models describing transistor behavior in all operating regimes including low levels of MOSFET channel inversion. In this paper, Leti-UTSOI based RF model will be compared against electrical measurements...
This paper shows SPICE simulation results of active guard ring structures which are typically employed in Smart Power ICs. Active guard rings act as barriers limiting the flow of minority carriers injected into the substrate toward sensitive circuits. The physical mechanisms involved in the active guard rings are confirmed with SPICE simulation for the first time and are in good agreement with those...
Smart Power IC integrating high voltage devices with low voltage control blocks becomes more and more popular in automotive industry recently. Minority carriers injected into the substrate during switching of high power stages cause malfunction of sensitive nearby low voltage devices. Sometimes this may be destructive due to the presence of triggered latch up. The minority carriers propagation is...
When designing in Smart Power technologies, TCAD simulations are mandatory to design effective passive protections against parasitic couplings due to minority carriers. The objective of this paper is to propose a spice-based approach to characterize electrical key parameters of a passive protection directly within standard IC design flow avoiding time consuming TCAD simulations. Our methodology consists...
The design of advanced integrated circuits (IC) in particular for low power analog and radio-frequency (RF) application becomes more complex as the device level modeling confronting challenges in micro- and nano-meter CMOS processes. As present CMOS technologies continue geometry scaling the designers can benefit using dedicated SPICE MOSFET models and apply specific analog design methodologies. The...
High voltage CMOS active devices inherently have a parasitic vertical bipolar transistor. The parasitic PNP structure can be activated during high-power switching operation causing a potential shift of the substrate. In this work a spice-modeling approach based on transistor layout is presented that is compatible with parasitic substrate noise propagation in Smart Power ICs. The results of the model...
In Smart Power ICs there is the need of new substrate models to be integrated in the design flow of power circuits. This work reports the latest results regarding the substrate modeling methodology based on three-dimensional lumped components extraction of diodes, resistors and contacts. The substrate network including lateral and vertical parasitic bipolar transistor can be automatically created...
In smart power IC technology, low and high voltage circuits are integrated on the same substrate. The commutation of the high voltage circuits can induce substrate parasitic currents which can severely disturb the operation of the low voltage circuits. The parasitic currents due to minority carriers in the high voltage technology can be significantly high. However, the minority carrier propagation...
Usually device compact models do not include breakdown mechanisms which are fundamental for ESD protection devices. This work proposes a novel spice-compatible modeling of breakdown phenomena for ESD diodes. The developed physics based approach includes minority carriers propagation and can be embedded in the simulation of parasitic substrate noise of power devices. The model implemented in VerilogA...
Minority carriers diffusion currents are particularly important in parasitic substrate couplings of Smart Power ICs. In CMOS technologies the P-substrate potential is imposed by P+ contacts and N-wells by N+ highly doped implantations. The doping concentration discontinuity of these contact regions can have a big impact on parasitic diffusion currents of minority carriers. This work gives a description...
This paper presents an equivalent electrical circuit for one dimensional substrate minority carriers spice simulation. The electrical circuit parameters are extracted from substrate meshing applying the finite difference method. This model is derived from a linearization of drift-diffusion equations and not from the closed form solution. Further, the proposed circuit is solved with available SPICE...
A new methodology for modeling minority carriers diffusion in Smart Power ICs substrate using standard circuit simulators has been proposed by EPFL. For this purpose, a parasitic substrate network consisting of lumped elements is extracted from the circuit layout following a given substrate meshing strategy. In this work Design of Experiments (DOE) techniques are used to run a limited number of simulations...
In this paper, we report for the first time, assessment on mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless (JL) nMOSFETs with cross-section down to 5 nm. This analysis was performed in accumulation regime, as a first step, addressing bias-dependency of various key MOSFET parameters (e.g. series resistance, channel width and gate-channel capacitance), non-uniform...
In this work, we present the technological constrains and limitations in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space that take into account the intrinsic off-current, the sub-threshold swing and the drain induced barrier lowering is investigated with respect to key technological parameters. This work could serve as a guideline for technology...
This paper reports an alternative simple fabrication process for twin gate junctionless Vertical Slit Field Effect Transistors. N-type devices have been successfully manufactured on SOI substrates with a doping density 5×1018 atoms/cm3. The devices demonstrate up to six decades of Ion/Ioff ratio and a sub-threshold swing of 90 mV/decade relative to a slit width of approximately 10 nm.
The current work focuses on presenting specific Hall cells with high performance, and their corresponding parameters. The design, integration, measurements and model development for their performance assessment are necessary stages considered in the generation of the Hall cells. Experimental results regarding the Hall cells absolute sensitivity, offset and offset temperature drift are provided for...
The present paper focuses on presenting the temperature effects on Hall Effect sensors sensitivity behavior. To this purpose, an analysis of the factors affecting the sensors current-related sensitivity is performed, consisting of several pertinent considerations. An analytical investigation of the carrier concentration temperature dependence including the freeze-out effect influence was performed...
In order to provide the information on their Hall voltage, sensitivity and drift with temperature, a new simpler lumped circuit model for the evaluation of various Hall Effect sensors has been developed. In this sense, the finite element model associated contains both geometrical parameters (dimensions of the cells) and physical parameters such as mobility, conductivity, Hall factor, carrier concentration...
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