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We report on a top-down fabricated nanowire RFET platform based on SOI substrates. Due to shell oxide induced strain it features the best symmetry of n- and p-type ON-currents for equal gate voltages reported so far. By this feature complementary reconfigurable circuits are enabled.
In this paper we describe an application example for our Manufacturing Assistant, a mobile robot assistant for future flexible manufacturing. The application, which is order-picking, was selected to demonstrate the Manufacturing Assistant’s capabilities for interactively learning new operation sequences. The sequence is taught using a laser pointer and a hand-held computer. Furthermore, the...
Intelligent mobile robot assistants are important components for increasing flexibility in future production processes. These robot assistants must be able to work autonomously but must also have the capability to interactively learn from and cooperate with the human worker in a common (shared) work space. They may never be a subject of danger to the human worker wherefore new methods for...
This 3-D TCAD study demonstrates a new stress element by strained isolation oxide for Tri-Gate and similar FinFET structures. The simulation shows an uniform improvement of N- and PMOS drive current (10 %) by using a tensile strained isolation material between the fins processed on standard (100) bulk wafer with <110> channel direction. Therefore it is a simple low-cost stress method for...
The impact of compressive and tensile stress on CMOS performance is studied for <100> and <110> oriented silicon and SiGe channels. The <110> channel direction is found to be more stress sensitive whereas the <100> oriented transistor has a higher initial hole mobility. These results recommend to use the <110> channel orientation for high performance application due to...
For future scaling to the end of the ITRS roadmap, novel structures like FinFETs are required to improve electrostatic integrity of MOSFETs with gate lengths shorter than 35 nm [1–4]. Classic fully-depleted FinFETs with a high aspect ratio are not compatible with existing planar process flows. A Tri-Gate transistor has the advantage of being more compatible. It is even possible to produce low-profile...
A hybrid Tri-Gate/planar process was investigated by 3-D process and device simulations. Electrostatics of a Tri-Gate and a planar transistor sharing the same well, halo, and S/D have been compared. The suppression of the Tri-Gate corner effect was studied by corner implantation and additional corner rounding after Tri-Gate fin formation. Corner implantation is useful for retargeting Tri-Gate threshold...
A Tri-Gate structure built into a planar 22 nm bulk process was investigated by 3-D device simulations (Sentaurus D-2010). The planar process flow sequence was extended with extra Tri-Gate patterning, but otherwise all implants were shared, as could be done in simultaneous processing of planar and Tri-Gate CMOS. A comparison of planar and Tri-Gate transistors with the same planar dopant profiles shows...
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