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This paper describes orthogonal scaling of dynamic-random-access-memories (DRAMs) using through-silicon-vias (TSVs). We review 3D DRAMs including DDR3, wide I/O mobile DRAM (WIDE I/O), and more recently, the hybrid-memory cube (HMC) and high-bandwidth memory (HBM) targeted for high-performance computing systems. We then cover embedded 3D DRAM for high-performance cache memories, reviewing an early...
An 80Kb logic Embedded Multi-Time Programmable Memory (MTPM) employs charge trapping and de-trapping behavior in 32nm/22nm High-K transistor, resulting in no added process complexity. Multi-step verification with overwrite protection employs block-write and signal margin degradation (∼30%) to satisfy 10 year retention at 105° C.
Reported for the first time is proof-of-concept multi-stacking of memory wafers based on low-temperature oxide wafer bonding using novel design and integration of two types of ultra-fine-dimension copper TSV interconnects. The combined via-middle (intra-via) and via-last (inter-via) strategy allows for the greatest degree of interconnectivity with the tightest allowable pitches and permits a highly...
For high-volume production of 3D-stacked chips with through-silicon-via (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology [1][2][3] and is promising for interconnect pitch <= 5μ range using available tooling. Prior work [3] has presented wafer-scale integration with tungsten TSV for low-power applications. This paper reports the first use of low-temperature...
For the first time we report a high performance embedded DRAM prototype fabricated in a 3D stackable 32nm High-K/Metal Gate technology with copper through-silicon vias. Post through-via processing functional test demonstrates that <1.5ns latency and 500MHz operation are preserved.
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