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In nanoscale CMOS process, integrated circuits (ICs) face serious gate reliability issues such as the damage of electrostatic discharge (ESD). The RC-triggered silicon-controlled rectifier (SCR) is widely studied for the high turn-on efficiency and discharge capability. However, the large gate leakage current of MOS capacitor in the traditional RC network in nanoscale process is not desired. In this...
The off-state leakage current characteristics of nano-scaled MOSFETs with high-k gate dielectric are thoroughly investigated. The off-state leakage current can be divided into three components and the influences of fringing induced barrier lowering (FIBL) effect and drain induced barrier lowering (DIBL) effect on each component are also investigated. For nano-scaled devices with high-k gates, the...
Degradation of electrical characteristics of NdAlO3/SiO2 stack gate under the constant voltage stress (CVS) is presented. It is found that the electron trapping, positive charges and oxide trap generation acts together, which causes the degradation of NdAlO3/SiO2 stack gate. The transport mechanisms of the gate leakage current in NdAlO3/SiO2 stack gate are also investigated. Frenkel-Poole emission...
We have used a remote-argon-plasma reactor in which the active species can be separated at a special plasma field. Argon gas is used as the work gas. In this remote argon plasma, the distribution of electrons, ions, and radicals and germicidal effect (GE) of Escherichia coli on the surface of medical poly(tetrafluoroethylene) (PTFE) film are studied. Then surface properties of sterilized PTFE are...
A learning method by recording cases based on an evaluation system for vessel collision avoidance is presented in this paper. The frame model is selected and defined as the case representation method. The basic structure and several processing modules of the evaluation system are discussed. Data fusion methods are used in the system. During processing of the learning case, fuzzy method is also adopted...
Stress in copper interconnects under the direct current (DC) and pulsed DC bias, considering the impact of barrier layer, is calculated numerically. The calculation results show that the barrier layer used to stop the copper diffusion also reduces the stress in interconnects. The extent in reduction of stress under DC case is higher than that under the pulsed DC bias
A modified model for electromigration transport considering the barrier layer effect is developed, based on the one-dimensional continuum model. Electromigration lifetime under the direct current (DC) and pulsed DC stress is analyzed numerically. The simulation results demonstrate that the barrier layer used to stop the copper diffusion also improves the interconnect lifetime. The improvement of lifetime...
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