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A low-voltage low-dropout (LDO) regulator that converts an input of 1 V to an output of 0.85–0.5 V, with 90-nm CMOS technology is proposed. A simple symmetric operational transconductance amplifier is used as the error amplifier (EA), with a current splitting technique adopted to boost the gain. This also enhances the closed-loop bandwidth of the LDO regulator. In the rail-to-rail output stage of...
Power gating technique is important for saving the leakage power, especially for the very deep-submicron system-on-a-chip designs. Although the multi-threshold voltage CMOS (MTCMOS) technology can enable us to cut down the leaky path easily, the induced power/ground bounce is getting worse and can not wake up from power down mode quickly. In this paper, we propose a new concept of power gating technique...
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