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A 140 MS/s 10-bit pipelined analog-to-digital converter (ADC) using a folded sample-and-hold (S/H) stage and a 5-bit flash ADC is presented. To conquer the limited linear swing range results from an operational amplifier (OP-AMP). The proposed folded S/H stage allows the ADC to operate in the linear swing range of an OP-AMP. Only 17 comparators are required for a 5-bit flash ADC. Corresponding digital...
An 8-bit 20-MS/s time-domain analog-to-digital data converter (ADC) using the zero-crossing-based circuit technique is presented. Compared with the conventional ADCs, signal processing is executed in both the voltage and time domains. Since no high-gain operational amplifier is needed, this time-domain ADC works well in a low supply voltage. The proposed ADC has been fabricated in a 0.18-mum CMOS...
A 1.5-bit/stage 8-bit 140MS/s pipelined ADC with folded sampled-and-hold stage is presented. The proposed technique improves the nonlinearity without using complicated calibration circuitry and neither does it require extra calibration cycle. Only 17 comparators are required for a 5-bit flash ADC. This 8-bit pipelined ADC has been fabricated in a 0.18 um CMOS process. It dissipates 39 mW with a supply...
A 7-bit 400 MS/s sub-ranging flash analog-to-digital data converter (ADC) with short latency is presented. To improve the sampling rate, the fine pre-amplifiers combined with the switched current sources are adopted instead of the switch matrix in a conventional sub-ranging ADC. The proposed architecture avoids the noise coupling from the switches and reduces the parasitic capacitances, which limit...
10-b resolution is achieved by applying the existing commutated feed-back capacitor switching (CFCS) technique. Capacitive loads in the transfer characteristics are reduced in critical pipeline stages, and single-phase latches are proposed to reduce the number of delay elements by half. In order to obtain the required clock driving capability, distributed clock generator is used. This prototype is...
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