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It is known that temperature gradients and thermal hotspots affect the reliability of microprocessors. Temperature is also an important constraint when maximizing the performance of processors. Although DVFS and DFS can be used to extract higher performance from temperature and power constrained single core processors, the full potential of multi-core performance cannot be exploited without the use...
This paper presents a new parallel processing wire routing machine, which finds a quasi-minimum Steiner tree for multi-point connections in a VLSI chip. A hardware implementation with concurrent time-multiplexed wavefront propagation from all terminals of a net is described. The new design requires fewer clock cycles to find the shortest path than the existing parallel routing algorithms. The time-multiplexed...
In this paper a 12-bit, 100-MSample/s current-steering CMOS D/A converter for wireless communication terminals is presented. Current steering DAC is used since, it is inherently fast and can drive the resistive load without using an output buffer. A segmented architecture is proposed to attain the required speed and accuracy. The INL and DNL of the DAC is less than 1LSB and is around 0.6 and 0.2 LSB...
The ability to fully leverage future CMOS technologies will require a proactive approach to aggressively manage power while characterizing and mitigating the various sources of technology uncertainty. Adaptive techniques that span the full design stack across technology, circuits, and systems/software are required for building future reliable systems. Moreover, the emerging trend of low-power, multi-core-based...
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