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Design and optimization of backside-thinned CMOS active pixel sensors (APS) using modeling and simulation is presented. For the efficient design and the further improvement of our backside-thinned CMOS imagers, different models were developed and TCAD simulating tools were used. The imagers have been successfully designed, fabricated and tested and proved to possess excellent imaging properties. This...
Increased buffer insertion along on-chip global lines and growing amounts of leakage power have resulted in buffer-based leakage emerging as one of the chief contributors to system leakage power. In this paper, a bus system prototype is implemented in an industrial 65-nm SOI technology and measured results show up to a 45% reduction in total bus system power and an average reduction of 2.4?? in standby...
With rapid advances in VLSI, technology has enabled us to reduce the minimum feature sizes of sub-quarter microns and the switching times to tens of picoseconds or even less. The trend in VLSI industry is moving toward designs that are more complex, higher operating frequencies, sharper rise times, shrinking device sizes and low power consumption. Although the device noise sources (i.e. shot noise,...
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